FIG. 1 (Prior Art) is a simplified diagram of a portion of a programmable logic device. An example of a programmable logic device is a field programmable gate array (FPGA). The programmable logic device includes a programmable interconnection structure 1 that can be programmed to couple a signal on a selected one of a plurality of vertically extending conductors 2–9 onto a horizontally extending conductor 10 such that the signal is communicated to the right to the G1 input lead of a configurable logic block (CLB) 11. One of a plurality of programmable interconnection points 12–19 is disposed at each crossing location where a vertically extending conductor crosses the horizontally extending conductor. Each programmable interconnection point includes a memory cell which determines whether the two crossing conductors are coupled together.
FIG. 2 (Prior Art) is a diagram illustrating one of the programmable interconnection points 12. It includes a memory cell and a transistor 20. Transistor 20 is coupled between vertically extending conductor 2 and horizontally extending conductor 10. If the memory cell contains a first digital logic value, then the transistor is controlled to be conductive such that the two crossing conductors are coupled together. If, on the other hand, the memory cell contains a second digital logic value, then the transistor is controlled to be non-conductive and the two crossing conductors are not coupled together.
To couple a signal on a selected one of vertically extending conductors 2–9 onto horizontally extending conductor 10, the programmable interconnection point at the intersection of the two conductors is programmed such that the two crossing conductors are coupled together. The programmable interconnection points located at the intersections of the other vertically extending conductors and the horizontally extending conductor are programmed such that their transistors are non-conductive. The structure of FIG. 1 can therefore be programmed to perform a multiplexer function in that the structure couples a signal on a selected one of the vertically extending conductors 2–9 onto the G1 input lead of CLB 11.
Although such a multiplexer structure in a programmable logic device is often illustrated and described as shown in FIGS. 1 and 2, the actual multiplexer structure may be implemented in several different ways on an actual integrated circuit. FIG. 3 is a simplified diagram of one possible implementation. This implementation involves a first stage of transmission gates 21, followed by a second stage of transmission gates 22, followed by an output buffer stage 23. Although the first transmission gate stage is illustrated with each of its transmission gates being controlled by its own dedicated memory cell, the first transmission gate stage is sometimes implemented in other ways. Sometimes there are fewer memory cells, and each of those memory cells controls two transmission gates, one in the upper group of four transmission gates and the other in the lower group of four transmission gates. Sometimes there are only two memory cells, and the outputs of the two memory cells are decoded to drive the eight transmission gates of the first stage.
Regardless of which of the many ways the multiplexer structure is implemented, a small gate leakage current 24 flows into the gate electrode of each of the transistors of the transmission gates. A small source-to-drain leakage current 25 also can flow through the transistors of the transmission gates. Although these leakage currents are small for an individual transmission gate, there are often a very large number of these multiplexer structures in a large state of the art programmable logic device. The combined leakage current for all the transmission gates of the programmable logic device can amount to a significant and undesirable leakage current.
To reduce the leakage current problem, the P-channel transistors of the transmission gates of FIG. 3 can be omitted. This eliminates the leakage current due to the P-channel transistors, but results in other unfortunate consequences. For example, a signal flowing through one of the N-channel transistors from left to right (for example, from input node 26 to intermediate node 27) will suffer a voltage drop of approximately one threshold voltage. The size of the signal is reduced, resulting in reduced noise margin and other problems. Moreover, the signal path from node 26 to node 27 is more resistive than the signal path would have otherwise been had conductive P-channel transistor 29 been connected in parallel with the N-channel transistor 28.
FIG. 4 (Prior Art) illustrates a problem associated with the increased resistance. The resistor symbol 30 represents the source-to-drain resistance between nodes 26 and 27 when P-channel transistor 29 is omitted. The capacitor symbol 31 represents the capacitance to ground of node 27. A signal passing from node 26 to node 27 is delayed due to the RC circuit. It is therefore seen that removing the P-channel transistors of the transmission gates of FIG. 3 improves the leakage current problem but gives rise to other problems. A solution is desired.